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DAC
2008
ACM
14 years 8 months ago
Symbolic noise analysis approach to computational hardware optimization
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
Arash Ahmadi, Mark Zwolinski
ICRA
2009
IEEE
112views Robotics» more  ICRA 2009»
14 years 2 months ago
Combining planning and motion planning
Abstract— Robotic manipulation is important for real, physical world applications. General Purpose manipulation with a robot (eg. delivering dishes, opening doors with a key, etc...
Jaesik Choi, Eyal Amir
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
14 years 1 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
14 years 3 days ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ATVA
2004
Springer
138views Hardware» more  ATVA 2004»
13 years 11 months ago
Providing Automated Verification in HOL Using MDGs
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
Tarek Mhamdi, Sofiène Tahar