1542 search results - page 14 / 309 » The Observational Power of Clocks |
RTAS
2000
IEEE
14 years 27 days ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
ISPD
1999
ACM
14 years 25 days ago
1999
ACM
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the tim...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response i...