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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 7 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
ICIP
2009
IEEE
14 years 11 months ago
Optimal Power Allocation For Minimizing Visual Distortion Over Mimo Communication Systems
A recent dynamic increase in demand for wireless multimedia services has greatly accelerated the research on cross layer optimization techniques for transmitting multimedia data o...
HIPEAC
2010
Springer
14 years 7 months ago
Performance and Power Aware CMP Thread Allocation Modeling
We address the problem of performance and power-efficient thread allocation in a CMP. To that end, based on analytical model, we introduce a parameterized performance/power metric ...
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
14 years 7 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
ASPDAC
2009
ACM
104views Hardware» more  ASPDAC 2009»
14 years 4 months ago
Addressing thermal and power delivery bottlenecks in 3D circuits
— The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footpr...
Sachin S. Sapatnekar