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RTCSA
2008
IEEE
14 years 2 months ago
Power-Aware Data Buffer Cache Management in Real-Time Embedded Databases
The demand for real-time data services in embedded systems is increasing. In these new computing platforms, using traditional buffer management schemes, whose goal is to minimize ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic
DAC
2002
ACM
14 years 9 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 5 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
LCTRTS
2007
Springer
14 years 2 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
14 years 1 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli