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1728
search results - page 15 / 346
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The Size of Power Automata
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DATE
2002
IEEE
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DATE 2002
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Sizing Power/Ground Meshes for Clocking and Computing Circuit Components
14 years 1 months ago
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Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malg...
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ISLPED
1998
ACM
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ISLPED 1998
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A power optimization method considering glitch reduction by gate sizing
14 years 21 days ago
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Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
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ICCAD
1993
IEEE
101
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ICCAD 1993
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Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
14 years 18 days ago
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Kerry S. Lowe, P. Glenn Gulak
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ICCAD
1995
IEEE
79
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ICCAD 1995
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Optimal wire sizing and buffer insertion for low power and a generalized delay model
14 years 14 hour ago
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John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin
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ASPDAC
2010
ACM
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ASPDAC 2010
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Buffered clock tree sizing for skew minimization under power and thermal budgets
13 years 6 months ago
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www.asp-dac.itri.org.tw
Krit Athikulwongse, Xin Zhao, Sung Kyu Lim
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