936 search results - page 28 / 188 » The Synthesis Problem of Netcharts |
DATE
2010
IEEE
14 years 24 days ago
2010
IEEE
Abstract—We propose a novel synthesis technique for reversible logic based on ant colony optimization (ACO). In our ACO-based approach, reversible logic synthesis is formulated a...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synt...
ISPD
2003
ACM
14 years 28 days ago
2003
ACM
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...