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DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 4 months ago
ILP Models for the Synthesis of Asynchronous Control Circuits
A new technique for the logic synthesis of asynchronous circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. The technique is ...
Josep Carmona, Jordi Cortadella
ICTAI
2002
IEEE
14 years 16 days ago
A Genetic Testing Framework for Digital Integrated Circuits
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabe...
ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
13 years 11 months ago
Fault simulation of interconnect opens in digital CMOS circuits
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Haluk Konuk
ISCAS
2006
IEEE
128views Hardware» more  ISCAS 2006»
14 years 1 months ago
Modeling and verification of high-speed wired links with Verilog-AMS
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
Ming-Ta Hsieh, Gerald E. Sobelman