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» The design of a 64-bit integer multiplier divider unit
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ICCD
2007
IEEE
746views Hardware» more  ICCD 2007»
14 years 4 months ago
Hardware design of a Binary Integer Decimal-based floating-point adder
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...
ARITH
1993
IEEE
13 years 11 months ago
The design of a 64-bit integer multiplier/divider unit
D. Eisig, J. Rotstain, I. Koren
ASAP
2007
IEEE
101views Hardware» more  ASAP 2007»
14 years 1 months ago
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754)....
Charles Tsen, Michael J. Schulte, Sonia Gonzalez-N...
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
DSD
2003
IEEE
69views Hardware» more  DSD 2003»
14 years 23 days ago
A VLIW Architecture for Logarithmic Arithmetic
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...
Mark G. Arnold