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» The design of a high performance low power microprocessor
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ERSA
2008
145views Hardware» more  ERSA 2008»
13 years 9 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
APCCAS
2006
IEEE
256views Hardware» more  APCCAS 2006»
14 years 1 months ago
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, ...
ASPDAC
2007
ACM
110views Hardware» more  ASPDAC 2007»
13 years 11 months ago
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
HPCA
2006
IEEE
14 years 7 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
CDES
2006
101views Hardware» more  CDES 2006»
13 years 9 months ago
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin