This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
—The success of server virtualization has let to the deployment of a huge number of virtual machines in today’s data centers, making a manual virtualization management very lab...
Matthias Bolte, Michael Sievers, Georg Birkenheuer...
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...