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DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 3 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 3 months ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 2 months ago
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
Ilya Issenin, Nikil D. Dutt
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
14 years 1 months ago
Non-intrusive virtualization management using libvirt
—The success of server virtualization has let to the deployment of a huge number of virtual machines in today’s data centers, making a manual virtualization management very lab...
Matthias Bolte, Michael Sievers, Georg Birkenheuer...
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
14 years 15 days ago
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...