Sciweavers

1476 search results - page 28 / 296
» Three-dimensional integrated circuits
Sort
View
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
15 years 8 months ago
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael ...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 10 months ago
Optimal sizing of configurable devices to reduce variability in integrated circuits
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) st...
Peter Wilson, Reuben Wilcock
DATE
2009
IEEE
134views Hardware» more  DATE 2009»
15 years 10 months ago
Massively multi-topology sizing of analog integrated circuits
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
Pieter Palmers, Trent McConaghy, Michiel Steyaert,...
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
15 years 8 months ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
ICCAD
2000
IEEE
171views Hardware» more  ICCAD 2000»
15 years 7 months ago
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is ...
Michael Pronath, Volker Gloeckel, Helmut E. Graeb