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ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
14 years 3 months ago
Low-Power Circuits for Brain-Machine Interfaces
—This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthe...
Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjami...
EVOW
2000
Springer
14 years 20 days ago
Prediction of Power Requirements for High-Speed Circuits
Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from f...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
14 years 2 months ago
Generalized Posynomial Performance Modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set ...
Tom Eeckelaert, Walter Daems, Georges G. E. Gielen...
TIM
2010
294views Education» more  TIM 2010»
13 years 3 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 1 months ago
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
Robert Schwencker, Josef Eckmueller, Helmut E. Gra...