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ICCAD
1999
IEEE
72views Hardware» more  ICCAD 1999»
14 years 1 months ago
An integrated algorithm for combined placement and libraryless technology mapping
This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless ma...
Yanbin Jiang, Sachin S. Sapatnekar
TCAD
2002
137views more  TCAD 2002»
13 years 8 months ago
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicouple
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
Yungseon Eo, Seongkyun Shin, William R. Eisenstadt...
ICCAD
2001
IEEE
97views Hardware» more  ICCAD 2001»
14 years 6 months ago
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiova...
DAC
2008
ACM
14 years 10 months ago
The mixed signal optimum energy point: voltage and parallelism
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...
Brian P. Ginsburg, Anantha P. Chandrakasan
ICCD
2008
IEEE
157views Hardware» more  ICCD 2008»
14 years 6 months ago
Power-aware soft error hardening via selective voltage scaling
—Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking...
Kai-Chiang Wu, Diana Marculescu