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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
1999
IEEE
153views Hardware» more  ICCAD 1999»
14 years 1 days ago
Cycle time and slack optimization for VLSI-chips
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
Christoph Albrecht, Bernhard Korte, Jürgen Sc...
DAC
2008
ACM
14 years 8 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 2 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
ISPD
2007
ACM
99views Hardware» more  ISPD 2007»
13 years 9 months ago
Minimal skew clock embedding considering time variant temperature gradient
The existing temperature-aware clock embedding assumes a time-invariant temperature gradient. However, it is not solved how to find the worst-case temperature gradient leading to...
Hao Yu, Yu Hu, Chunchen Liu, Lei He
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
14 years 1 months ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan