4306 search results - page 155 / 862 » Timed Testing with TorX |
DATE
1999
IEEE
14 years 2 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-achip (SOC) environment. The main novelty of the approach is the...
VTS
2000
IEEE
14 years 2 months ago
2000
IEEE
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
ICCAD
2008
IEEE
14 years 7 months ago
2008
IEEE
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
— In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-...