57 search results - page 9 / 12 » Timing metrics for physical design of deep submicron technol... |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
ISVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
ISPD
2003
ACM
14 years 18 days ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
ISPD
2005
ACM
14 years 27 days ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...