This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...
Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabae...