51 search results - page 6 / 11 » Timing variation-aware high-level synthesis |
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
ISSS
1999
IEEE
13 years 11 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...