120 search results - page 8 / 24 » Timing-driven placement for FPGAs |
FPGA
1999
ACM
13 years 12 months ago
1999
ACM
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
GLVLSI
2000
IEEE
14 years 3 days ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
FPGA
2003
ACM
14 years 28 days ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...
DATE
2000
IEEE
14 years 3 days ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...