300 search results - page 23 / 60 » Tools and Methodologies for Low Power Design |
126
Voted
ICCAD
1999
IEEE
15 years 7 months ago
1999
IEEE
Design systems to provide various quality of service (QoS) guarantees has received a lot of attentions due to the increasing popularity of real-time multimedia and wireless commun...
146
click to vote
ISQED
2006
IEEE
15 years 9 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
113
Voted
ICCAD
2003
IEEE
16 years 9 days ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
108
Voted
DAC
2006
ACM
15 years 9 months ago
2006
ACM
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
134
click to vote
DAC
1998
ACM
16 years 4 months ago
1998
ACM
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is ...