13 search results - page 2 / 3 » Transistor-Specific Delay Modeling for SSTA |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important th...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...