524 search results - page 8 / 105 » Two efficient methods to reduce power and testing time |
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
PPOPP
2005
ACM
14 years 27 days ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
CVPR
2008
IEEE
14 years 9 months ago
2008
IEEE
In this paper, we present novel techniques that improve the computational and memory efficiency of algorithms for solving multi-label energy functions arising from discrete MRFs o...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...