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» Understanding POWER multiprocessors
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NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
14 years 1 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
TDSC
2010
111views more  TDSC 2010»
13 years 7 months ago
Using Underutilized CPU Resources to Enhance Its Reliability
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Sur...
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
13 years 23 days ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
HPCA
2006
IEEE
14 years 9 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
EMSOFT
2005
Springer
14 years 2 months ago
High-level real-time programming in Java
Real-time systems have reached a level of complexity beyond the scaling capability of the low-level or restricted languages traditionally used for real-time programming. While Met...
David F. Bacon, Perry Cheng, David Grove, Michael ...