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» Using BIST Control for Pattern Generation
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VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 1 months ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
ISCAS
2007
IEEE
164views Hardware» more  ISCAS 2007»
14 years 1 months ago
Noise Figure Measurement Using Mixed-Signal BIST
—A Built-In Self-Test (BIST) approach for functionality measurements, including noise figure (NF), linearity and frequency response of analog circuitry in mixedsignal systems, is...
Jie Qin, Charles E. Stroud, Foster F. Dai
VLSID
2005
IEEE
120views VLSI» more  VLSID 2005»
14 years 1 months ago
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattachar...
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
13 years 11 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
VTS
1997
IEEE
73views Hardware» more  VTS 1997»
13 years 11 months ago
Obtaining High Fault Coverage with Circular BIST Via State Skipping
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...
Nur A. Touba