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» Using Eigenvectors to Partition Circuits
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DAC
1999
ACM
14 years 27 days ago
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
DAC
1996
ACM
14 years 22 days ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
14 years 23 days ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
ITC
2003
IEEE
124views Hardware» more  ITC 2003»
14 years 1 months ago
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding
We propose a procedure for designing an LFSRbased circuit for masking of unknown output values that appear in the output response of a circuit tested using LBIST. The procedure is...
Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, S...
ISCAS
1999
IEEE
126views Hardware» more  ISCAS 1999»
14 years 26 days ago
Applications of clone circuits to issues in physical-design
In a companion paper of this session [1] we formally defined the notion of equivalence classes of circuits which are physical clones of an existing benchmark seed circuit created ...
Michael D. Hutton, Jonathan Rose