: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
We propose a procedure for designing an LFSRbased circuit for masking of unknown output values that appear in the output response of a circuit tested using LBIST. The procedure is...
Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, S...
In a companion paper of this session [1] we formally defined the notion of equivalence classes of circuits which are physical clones of an existing benchmark seed circuit created ...