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SIPS
2006
IEEE
14 years 2 months ago
Automated Architectural Exploration for Signal Processing Algorithms
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 5 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
SCP
2010
163views more  SCP 2010»
13 years 3 months ago
Compact and efficient strings for Java
In several Java VMs, strings consist of two separate objects: metadata such as the string length are stored in the actual string object, while the string characters are stored in ...
Christian Häubl, Christian Wimmer, Hanspeter ...
MICRO
2008
IEEE
149views Hardware» more  MICRO 2008»
14 years 3 months ago
Prefetch-Aware DRAM Controllers
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N...
VTS
2003
IEEE
95views Hardware» more  VTS 2003»
14 years 2 months ago
Built-In Reseeding for Serial Bist
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...
Ahmad A. Al-Yamani, Edward J. McCluskey