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» Using embedded FPGAs for SoC yield improvement
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FPL
2006
Springer
219views Hardware» more  FPL 2006»
13 years 11 months ago
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
François-Xavier Standaert, Gaël Rouvro...
FPT
2005
IEEE
98views Hardware» more  FPT 2005»
14 years 1 months ago
Secure Partial Reconfiguration of FPGAs
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
Amir Sheikh Zeineddini, Kris Gaj
MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
14 years 20 days ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
14 years 1 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
DAC
2006
ACM
14 years 8 months ago
Architecture-aware FPGA placement using metric embedding
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...