428 search results - page 33 / 86 » Validating High-Level Synthesis |
ISLPED
2003
ACM
14 years 4 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ISSS
1999
IEEE
14 years 3 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
ICCAD
1997
IEEE
14 years 3 months ago
1997
IEEE
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
FCCM
2011
IEEE
13 years 2 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
DATE
2000
IEEE
14 years 3 months ago
2000
IEEE
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...