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» Variation-tolerant circuits: circuit solutions and technique...
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ACSD
2004
IEEE
113views Hardware» more  ACSD 2004»
14 years 7 days ago
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
14 years 21 days ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
14 years 10 days ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 3 months ago
Trace signal selection for visibility enhancement in post-silicon validation
Today’s complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from presilicon verification. One effective silicon debug ...
Xiao Liu, Qiang Xu
DAC
2008
ACM
14 years 9 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes