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» Verifying VLSI Circuits
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VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
14 years 9 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
VLSID
2004
IEEE
114views VLSI» more  VLSID 2004»
14 years 9 months ago
High-Speed Optoelectronics Receivers in SiGe
This paper focuses on the investigation of integrated CMOS and Silicon/Germanium (SiGe) devices for highspeed optical receiver circuits. In this paper, we present several competit...
Amit Gupta, Steven P. Levitan, Leo Selavo, Donald ...
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
14 years 9 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
VLSID
2002
IEEE
124views VLSI» more  VLSID 2002»
14 years 9 months ago
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods
We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a statespace model where t...
Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
ICCD
2002
IEEE
160views Hardware» more  ICCD 2002»
14 years 5 months ago
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams
We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining ...
Sanjukta Bhanja, N. Ranganathan