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    DAC
    1994
    ACM
    120views Computer Architecture» more  DAC 1994»
    Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits
    13 years 11 months ago
    Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits
    Download  www.cecs.uci.edu
    A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...
    Sharad Mehrotra, Paul D. Franzon, Wentai Liu
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    ICCD
    2001
    IEEE
    213views Hardware» more  ICCD 2001»
    Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
    14 years 4 months ago
    Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
    Download  www.ece.uci.edu
    Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
    Payam Heydari, Massoud Pedram
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    ASPDAC
    1999
    ACM
    113views Hardware» more  ASPDAC 1999»
    An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
    13 years 12 months ago
    An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
    Download  www.cs.york.ac.uk
    In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
    C. K. Eem, J. W. Chong
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    DAC
    1999
    ACM
    149views Computer Architecture» more  DAC 1999»
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
    13 years 12 months ago
    Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
    Download  www.cecs.uci.edu
    Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
    Vijay Sundararajan, Keshab K. Parhi
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    EURODAC
    1994
    IEEE
    209views VHDL» more  EURODAC 1994»
    MOS VLSI circuit simulation by hardware accelerator using semi-natural models
    13 years 11 months ago
    MOS VLSI circuit simulation by hardware accelerator using semi-natural models
    Download  www.cs.york.ac.uk
    - The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
    Victor V. Denisenko
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