222 search results - page 13 / 45 » Verifying an Arbiter Circuit |
DATE
2010
IEEE
13 years 8 months ago
2010
IEEE
The Monte Carlo (MC) simulation is a well-known solution to the statistical analysis of analog circuits in the presence of device mismatch. Despite MC's superior accuracy comp...
ASPDAC
2007
ACM
13 years 12 months ago
2007
ACM
-- Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits us...
DATE
2010
IEEE
14 years 8 days ago
2010
IEEE
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
ICCAD
1994
IEEE
14 years 1 days ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...