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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
14 years 3 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
DATE
2010
IEEE
182views Hardware» more  DATE 2010»
14 years 3 months ago
Fault-based attack of RSA authentication
For any computing system to be secure, both hardware and software have to be trusted. If the hardware layer in a secure system is compromised, not only it would be possible to ext...
Andrea Pellegrini, Valeria Bertacco, Todd M. Austi...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
14 years 3 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 3 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
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