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    TODAES
    2008
    69views more  TODAES 2008»
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    15 years 7 months ago
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    Download  www.ee.ucla.edu
    Yu Hu, Yan Lin, Lei He, Tim Tuan
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    TRETS
    2008
    42views more  TRETS 2008»
    On the trade-off between power and flexibility of FPGA clock networks
    15 years 7 months ago
    On the trade-off between power and flexibility of FPGA clock networks
    Download  www.ece.ubc.ca
    Julien Lamoureux, Steven J. E. Wilton
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    99
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    TRETS
    2008
    46views more  TRETS 2008»
    Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
    15 years 7 months ago
    Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
    Download  cas.ee.ic.ac.uk
    N. Pete Sedcole, Peter Y. K. Cheung
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    TCAD
    1998
    101views more  TCAD 1998»
    An efficient algorithm for performance-optimal FPGA technology mapping with retiming
    15 years 7 months ago
    An efficient algorithm for performance-optimal FPGA technology mapping with retiming
    Download  cadlab.cs.ucla.edu
    Jason Cong, Chang Wu
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    TVLSI
    1998
    64views more  TVLSI 1998»
    Effect of the prefabricated routing track distribution on FPGA area-efficiency
    15 years 7 months ago
    Effect of the prefabricated routing track distribution on FPGA area-efficiency
    Download  www.eecg.toronto.edu
    Vaughn Betz, Jonathan Rose
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