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259
search results - page 4 / 52
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fpga 2008
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TODAES
2008
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TODAES 2008
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Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
13 years 9 months ago
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www.ee.ucla.edu
Yu Hu, Yan Lin, Lei He, Tim Tuan
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12
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TRETS
2008
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TRETS 2008
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On the trade-off between power and flexibility of FPGA clock networks
13 years 9 months ago
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www.ece.ubc.ca
Julien Lamoureux, Steven J. E. Wilton
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9
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TRETS
2008
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TRETS 2008
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Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
13 years 9 months ago
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cas.ee.ic.ac.uk
N. Pete Sedcole, Peter Y. K. Cheung
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19
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TCAD
1998
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TCAD 1998
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An efficient algorithm for performance-optimal FPGA technology mapping with retiming
13 years 9 months ago
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cadlab.cs.ucla.edu
Jason Cong, Chang Wu
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TVLSI
1998
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TVLSI 1998
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Effect of the prefabricated routing track distribution on FPGA area-efficiency
13 years 9 months ago
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www.eecg.toronto.edu
Vaughn Betz, Jonathan Rose
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