Software development and testing of Enterprise Resource Planning (ERP) systems demands dedicated methods to tackle its special features. As manual testing is not able to systematic...
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
This paper describes an OMAP-based real-time test bench to find the Pareto frontier of an H.264/SVC decoder within a distortion-energy optimization space. A metric to estimate vide...
F. Pescador, E. Juarez, D. Samper, C. Sanz, Micka&...
Until a decade ago, the concept of phased array beamforming was mainly implemented with mechanical or analog solutions. Today, digital hardware has become powerful enough to perfor...
Marcel D. van de Burgwal, Kenneth C. Rovers, Koen ...
Orthogonal Frequency Division Multiplexing (OFDM) can provide a flexible usage of the spectrum by controlling individual subcarriers. Sets of subcarriers can be zero-modulated to a...
The H.264/AVC video encoder standard significantly improves the compression efficiency by using variable block-sized Inter (P) and Intra (I) Macroblock (MB) coding modes. In this p...
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...