Reconfigurable computing (RC) applications have the potential for significant performance while consuming little power. Although runtime performance analysis of RC applications has...
Research in communication networks has shown that the Internet architecture is not sufficient for modern communication areas such as the interconnection networks of super computing...
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly imp...
The pixel purity index algorithm is employed in remote sensing for analyzing hyperspectral images. A single pixel usually covers several different materials, and its observed spect...
In this paper, we introduce the open-source PivPav backend tool for reconfigurable computing. Essentially, PivPav provides an interface to a library of digital circuits that are ke...
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Abstract. Current mobile digital communication systems must implement rigorous operations to guarantee high levels of confidentiality and integrity during transmission of critical ...
In classical data warehouses (DWH), classification of values takes place in a sharp manner, because of this true values cannot be measured and smooth transition between classes do...