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ACSD
2006
IEEE
109views Hardware» more  ACSD 2006»
14 years 1 months ago
Synthesis of Synchronous Interfaces
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
Purandar Bhaduri, S. Ramesh
IWMM
2010
Springer
211views Hardware» more  IWMM 2010»
14 years 1 months ago
Concurrent, parallel, real-time garbage-collection
With the current developments in CPU implementations, it becomes obvious that ever more parallel multicore systems will be used even in embedded controllers that require real-time...
Fridtjof Siebert
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
14 years 1 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
14 years 1 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
14 years 1 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
ISQED
2010
IEEE
161views Hardware» more  ISQED 2010»
14 years 1 months ago
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedr...
ISPD
2010
ACM
156views Hardware» more  ISPD 2010»
14 years 1 months ago
Ultra-fast interconnect driven cell cloning for minimizing critical path delay
Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan ...
ISMVL
2010
IEEE
161views Hardware» more  ISMVL 2010»
14 years 1 months ago
Revisiting Ultraproducts in Fuzzy Predicate Logics
—In this paper we examine different possibilities of defining reduced products and ultraproducts in fuzzy predicate logics. We present analogues to the Łos Theorem for these no...
Pilar Dellunde
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 1 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner