This paper describes the unrolling of loops with indeterminate loop counts in system level pipelines. Two methods are discussed in this paper. The first method is the varied latenc...
Abstract -- This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Detail...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
— The paper introduces a novel co-compiler and its “vertical” parallelization method, including a general model for co-operating host/accelerator platforms and a new parallel...
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
In this paper I examine what industry really needs from formal specification techniques. I first describe the background to our use of formal techniques. I then look at the role o...
The Unified Modeling Language (UML) is likely to become an important industry standard language for modelling object-oriented systems. However, its use as a precise analysis tool ...
A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-to...
Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wu...