This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu,...
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
This paper evaluates several mechanisms for repairing the return-address stack after branch mispredictions. The return-address stack is a small but important structure for achievi...
Kevin Skadron, Pritpal S. Ahuja, Margaret Martonos...