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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 9 months ago
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 9 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 9 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 9 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
MICRO
2010
IEEE
170views Hardware» more  MICRO 2010»
13 years 9 months ago
Tolerating Concurrency Bugs Using Transactions as Lifeguards
Abstract--Parallel programming is hard, because it is impractical to test all possible thread interleavings. One promising approach to improve a multi-threaded program's relia...
Jie Yu, Satish Narayanasamy
ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
13 years 9 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
Derek Chan, Matthew R. Guthaus
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
13 years 9 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 9 months ago
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Abstract--As a replacement for the fast-fading GloballySynchronous model, we have defined a flexible design style called GRLS, for Globally-Ratiochronous, Locally-Synchronous, whic...
Jean-Michel Chabloz, Ahmed Hemani
ISLPED
2010
ACM
234views Hardware» more  ISLPED 2010»
13 years 9 months ago
Diet SODA: a power-efficient processor for digital cameras
Power has become the most critical design constraint for embedded handheld devices. This paper proposes a power-efficient SIMD architecture, referred to as Diet SODA, for DSP appl...
Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chait...
IMC
2010
ACM
13 years 9 months ago
Comparing and improving current packet capturing solutions based on commodity hardware
Capturing network traffic with commodity hardware has become a feasible task: Advances in hardware as well as software have boosted off-the-shelf hardware to performance levels th...
Lothar Braun, Alexander Didebulidze, Nils Kammenhu...