ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Three-dimensional (3D) memory products are emerging to fulfill the ever-increasing demands of storage capacity. In 3D-stacked memory, redundancy sharing between neighboring vertic...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Categories and Subject Descriptors Keywords .
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Tow...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
This paper is concerned with finding timing-independent false paths that cannot be sensitized under any signal arrival time condition in integrated circuits. Existing techniques r...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
ICCAD
2010
IEEE
13 years 9 months ago
2010
IEEE
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...