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FCCM
2009
IEEE
204views VLSI» more  FCCM 2009»
14 years 3 months ago
Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs
Geometric algebra (GA) is a mathematical framework that allows the compact description of geometric relationships and algorithms in many fields of science and engineering. The exe...
Holger Lange, Florian Stock, Andreas Koch, Dietmar...
FCCM
2009
IEEE
316views VLSI» more  FCCM 2009»
14 years 3 months ago
An FPGA Implementation for Solving Least Square Problem
This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...
Depeng Yang, Gregory D. Peterson, Husheng Li, Junq...
FCCM
2009
IEEE
136views VLSI» more  FCCM 2009»
14 years 3 months ago
Accelerating Cosmological Data Analysis with FPGAs
Volodymyr V. Kindratenko, Robert J. Brunner
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
14 years 3 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
14 years 3 months ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
14 years 3 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
14 years 3 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 3 months ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei