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    VLSID
    1993
    IEEE
    133views VLSI» more  VLSID 1993»
    An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
    14 years 3 months ago
    An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
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    An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
    V. Visvanathan, Nibedita Mohanty, S. Ramanathan
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    VLSID
    1993
    IEEE
    136views VLSI» more  VLSID 1993»
    A Simulation-Based Test Generation Scheme Using Genetic Algorithms
    14 years 3 months ago
    A Simulation-Based Test Generation Scheme Using Genetic Algorithms
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    This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
    M. Srinivas, Lalit M. Patnaik
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    VLSID
    1993
    IEEE
    114views VLSI» more  VLSID 1993»
    A Methodology for Generating Application Specific Tree Multipliers
    14 years 3 months ago
    A Methodology for Generating Application Specific Tree Multipliers
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    Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...
    S. Ramanathan, Nibedita Mohanty, V. Visvanathan
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    VLSID
    1993
    IEEE
    234views VLSI» more  VLSID 1993»
    NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
    14 years 3 months ago
    NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
    Download  eprints.iisc.ernet.in
    High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
    Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....
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    DFT
    1994
    IEEE
    157views VLSI» more  DFT 1994»
    An Approach to the Development of a IDDQ Testable Cell Library
    14 years 3 months ago
    An Approach to the Development of a IDDQ Testable Cell Library
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    C. Ferrer, D. Dateo, J. Oliver, Antonio Rubio, M. ...
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    DFT
    1994
    IEEE
    102views VLSI» more  DFT 1994»
    Laser Processes for Defect Correction in Large Area VLSI Systems
    14 years 3 months ago
    Laser Processes for Defect Correction in Large Area VLSI Systems
    Download  deneb.ensc.sfu.ca
    Glenn H. Chapman
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    DFT
    1994
    IEEE
    121views VLSI» more  DFT 1994»
    Reconfiguration in 3D Meshes
    14 years 3 months ago
    Reconfiguration in 3D Meshes
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    The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
    Anuj Chandra, Rami G. Melhem
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    DFT
    1993
    IEEE
    93views VLSI» more  DFT 1993»
    Layout Level Design for Testability Strategy Applied to a CMOS Cell Library
    14 years 3 months ago
    Layout Level Design for Testability Strategy Applied to a CMOS Cell Library
    Download  doc.utwente.nl
    M. Rullán, F. C. Blom, J. Oliver, C. Ferrer
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    DFT
    1993
    IEEE
    90views VLSI» more  DFT 1993»
    High Level Synthesis Techniques for Efficient Built-In-Self Repair
    14 years 3 months ago
    High Level Synthesis Techniques for Efficient Built-In-Self Repair
    Download  www.cs.ucla.edu
    Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
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    DFT
    1993
    IEEE
    93views VLSI» more  DFT 1993»
    Neural Networks for Multiple Fault Diagnosis in Analog Circuits
    14 years 3 months ago
    Neural Networks for Multiple Fault Diagnosis in Analog Circuits
    Download  bode.diee.unica.it
    Alessandra Fanni, Alessandro Giua, Enrico Sandoli
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