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GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
GLVLSI
2009
IEEE
146views VLSI» more  GLVLSI 2009»
14 years 2 months ago
A reconfigurable stochastic architecture for highly reliable computing
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan...
GLVLSI
2009
IEEE
172views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Contact merging algorithm for efficient substrate noise analysis in large scale circuits
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
Michael Kadin, Sherief Reda, Augustus K. Uht
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
14 years 2 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Spatial and temporal design debug using partial MaxSAT
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
Yibin Chen, Sean Safarpour, Andreas G. Veneris, Jo...
GLVLSI
2009
IEEE
151views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Reliability aware NoC router architecture using input channel buffer sharing
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Mohammad Hossein Neishaburi, Zeljko Zilic
FCCM
2009
IEEE
322views VLSI» more  FCCM 2009»
14 years 2 months ago
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)
Abstract--The Cibola Flight Experiment (CFE) is an experimental small satellite developed at the Los Alamos National Laboratory to demonstrate the feasibility of using FPGA-based r...
Michael P. Caffrey, Keith Morgan, Diane Roussel-Du...
FCCM
2009
IEEE
147views VLSI» more  FCCM 2009»
14 years 2 months ago
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
Artificial neural networks are a key tool for researchers attempting to understand and replicate the behaviour and intelligence found in biological neural networks. Software simul...
David Thomas, Wayne Luk