Sciweavers

FCCM
2007
IEEE
485views VLSI» more  FCCM 2007»
14 years 3 months ago
Low-Cost Stereo Vision on an FPGA
We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation uti...
Chris Murphy, Daniel Lindquist, Ann Marie Rynning,...
FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
14 years 3 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
DFT
2007
IEEE
152views VLSI» more  DFT 2007»
14 years 3 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...
VLSID
1994
IEEE
113views VLSI» more  VLSID 1994»
14 years 3 months ago
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs
In this paper, we propose an architecture synthesis methodolog `to realize cascaded Infinite Impulse Response (IIRJfilter in Table Look Up (TLU) Field Progmmmable Gate A m y s (FP...
G. N. Rathna, S. K. Nandy, K. Parthasarathy
VLSID
1994
IEEE
82views VLSI» more  VLSID 1994»
14 years 3 months ago
High Speed Digital Filtering on SRAM-Based FPGAs
A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghosha...
VLSID
1994
IEEE
124views VLSI» more  VLSID 1994»
14 years 3 months ago
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
Samit Chaudhuri, Robert A. Walker
VLSID
1994
IEEE
84views VLSI» more  VLSID 1994»
14 years 3 months ago
Energy Efficient Programmable Computation
: This paper describes techniques for energy efficient implementation of programmable computation. consumption in programmable computation can be substantiallvlowered with nolossin...
Anantha Chandrakasan, Mani B. Srivastava, Robert W...
VLSID
1994
IEEE
151views VLSI» more  VLSID 1994»
14 years 3 months ago
A CORDIC Based Programmable DXT Processor Array
A CORDIC based processor array which can be programmed by switch settings to compute the Discrete Hariley, Cosine or Sine lhnsforms or their inverses is described. Through a novel...
V. K. Anuradha, V. Visvanathan
VLSID
1994
IEEE
103views VLSI» more  VLSID 1994»
14 years 3 months ago
GLOVE: A Graph-Based Layout Verifier
Cyrus Bamji, Jonathan Allen