VLSID
2000
IEEE
13 years 11 months ago
2000
IEEE
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
VLSID
2000
IEEE
13 years 11 months ago
2000
IEEE
Digital images are convenient media for describing and storing spatial, temporal, spectral, and physical components of information contained in a variety of domains(e.g. aerial/sa...
VLSID
2000
IEEE
13 years 11 months ago
2000
IEEE
VLSID
2000
IEEE
13 years 11 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal...
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables,...