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FCCM
1999
IEEE
122views VLSI» more  FCCM 1999»
14 years 3 months ago
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
Andrew A. Chien, Jay H. Byun
FCCM
1999
IEEE
111views VLSI» more  FCCM 1999»
14 years 3 months ago
Optimizing FPGA-Based Vector Product Designs
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
Dan Benyamin, John D. Villasenor, Wayne Luk
FCCM
1999
IEEE
119views VLSI» more  FCCM 1999»
14 years 3 months ago
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor
Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald ...
DFT
1999
IEEE
119views VLSI» more  DFT 1999»
14 years 3 months ago
RAMSES: A Fast Memory Fault Simulator
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...
Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
DFT
1999
IEEE
80views VLSI» more  DFT 1999»
14 years 3 months ago
Determination of Yield Bounds Prior to Routing
Integrated Circuit manufacturing complexities have resulted in decreasing product yields and reliabilities. This process has been accelerated with the advent of very deep sub-micr...
Arunshankar Venkataraman, Israel Koren
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
14 years 3 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
DFT
1999
IEEE
139views VLSI» more  DFT 1999»
14 years 3 months ago
Soft-Error Detection through Software Fault-Tolerance Techniques
The paper describes a systematic approach for automatically introducing data and code redundancy into an existing program written using a high-level language. The transformations ...
Maurizio Rebaudengo, Matteo Sonza Reorda, Marco To...
DFT
1999
IEEE
72views VLSI» more  DFT 1999»
14 years 3 months ago
Yield Estimation of VLSI Circuits with Downscaled Layouts
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...
Witold A. Pleskacz
DFT
1999
IEEE
75views VLSI» more  DFT 1999»
14 years 3 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
14 years 3 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...