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GLVLSI
2000
IEEE
113views VLSI» more  GLVLSI 2000»
13 years 12 months ago
A novel technique for sea of gates global routing
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
GLVLSI
2000
IEEE
90views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Low power high speed analog-to-digital converter for wireless communications
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
A. E. Hussein, Mohamed I. Elmasry
GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
13 years 12 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
GLVLSI
2000
IEEE
82views VLSI» more  GLVLSI 2000»
13 years 12 months ago
A comparative study of power efficient SRAM designs
Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane...
GLVLSI
2000
IEEE
75views VLSI» more  GLVLSI 2000»
13 years 12 months ago
A wave-pipelined router architecture using ternary associative memory
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
José G. Delgado-Frias, Jabulani Nyathi, Lax...
GLVLSI
2000
IEEE
109views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Accuracy management for mixed-mode digital VLSI simulation
Gary L. Dare, Charles A. Zukowski
GLVLSI
2000
IEEE
83views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Power estimation for a submicron CMOS inverter driving a CRC interconnect load
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Hung-Jung Chen, Bradley S. Carlson
GLVLSI
2000
IEEE
69views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Supporting system-level power exploration for DSP applications
System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional b...
Luca Benini, Marco Ferrero, Alberto Macii, Enrico ...