VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is diffic...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverages. The very important class of dynamic fault, therefore cannot be ignored an...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE