VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
VTS
2002
IEEE
14 years 4 months ago
2002
IEEE
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
à This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic t...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...