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VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 1 months ago
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
Amir Attarha, Mehrdad Nourani
VTS
2002
IEEE
106views Hardware» more  VTS 2002»
14 years 1 months ago
How Effective are Compression Codes for Reducing Test Data Volume?
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
Anshuman Chandra, Krishnendu Chakrabarty, Rafael A...
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
14 years 1 months ago
Minimizing Energy Consumption for High-Performance Processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
14 years 1 months ago
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 1 months ago
An Adaptive Interconnect-Length Driven Placer
Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-B...
VLSID
2002
IEEE
81views VLSI» more  VLSID 2002»
14 years 1 months ago
A New Synthesis of Symmetric Functions
A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this...
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattac...
VLSID
2002
IEEE
192views VLSI» more  VLSID 2002»
14 years 1 months ago
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems
à This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic t...
Jiong Luo, Niraj K. Jha
VLSID
2002
IEEE
96views VLSI» more  VLSID 2002»
14 years 1 months ago
Strategies for Improving Data Locality in Embedded Applications
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, ...
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
14 years 1 months ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai